Modification in the Construction of Non-Binary LDPC Decoder using Stochastic Computation

Low-Density Parity Check (LDPC) codes are linear block codes which perform closer to Shannon‟s limit. It is defined by the parity check matrix (PCM) which contains only a few ones in comparison to the number of zeros (sparsity). Stochastic based computation is a method to design lowprecision digital circuits. In stochastic computing, probabilities are encoded by random sequences of bits. In this paper, we focus on the design of Relaxed Half Stochastic (RHS) based algorithm for Non-Binary LDPC decoder, with reduced hardware complexity and optimal decoding performance. Here Sum Product Algorithm (SPA) based variable nodes and stochastic based check nodes are integrated. Thereby the convergence speed of the algorithm is improved. The limitation of the complete stochastic decoder is based on the field order and the degree of variable node. This could be overcome by the method of RHS algorithm. The PCM (Parity Check Matrix) which defines the strength of the LDPC codes contains the non-zero elements. Increasing the sparsity of the PCM, helps in reducing the computation complexity. We propose two modifications in the PCM namely, LDM (Lower Diagonal Matrix) and DDM (Doubly Diagonal Matrix). Decoding performance measured in terms of bit error rate shows that non binary LDPC decoder outperforms than binary LDPC decoder. General Terms Algorithms, Decoder.